Abstract
Building memory protection mechanisms into embedded hardware is attractive because it has the potential to neutralize a host of software-based attacks with relatively small performance overhead. A hardware monitor, being at the lowest level of the system stack, is more difficult to bypass than a software monitor and hardware-based protections are also potentially more fine-grained than is possible in software: an individual instruction executing on a processor may entail multiple memory accesses, all of which may be tracked in hardware. Finally, hardware-based protection can be performed without the necessity of altering application binaries. This article presents a proof-of-concept codesign of a small embedded processor with a hardware monitor protecting against ROP-style code reuse attacks. While the case study is small, it indicates, we argue, an approach to rapid-prototyping runtime monitors in hardware that is quick, flexible, and extensible as well as being amenable to formal verification.
| Original language | American English |
|---|---|
| Title of host publication | 2018 International Symposium on Rapid System Prototyping (RSP) |
| Publisher | IEEE |
| Pages | 42-48 |
| Number of pages | 7 |
| ISBN (Print) | 978-1-5386-7558-8 |
| DOIs | |
| State | Published - Oct 5 2018 |
| Externally published | Yes |
| Event | 2018 International Symposium on Rapid System Prototyping (RSP) - Turin, Italy Duration: Oct 4 2018 → Oct 5 2018 |
Conference
| Conference | 2018 International Symposium on Rapid System Prototyping (RSP) |
|---|---|
| Period | 10/4/18 → 10/5/18 |
Keywords
- Monitoring
- Hardware
- Semantics
- Instruction sets
- Biomedical monitoring
- Runtime
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