Abstract
Verification of hardware-based cryptographic accelerators connects a low-level RTL implementation to the abstract algorithm itself; generally, the more optimized for performance an accelerator is, the more challenging its verification. This paper introduces a verification methodology, model validation, that uses a formalized high-level synthesis language (FHLS) as an intermediary between algorithm specification and hardware implementation. The foundation of our approach to model validation is a mechanized denotational semantics for the ReWire HLS language. Model validation proves the faithfulness of FHLS models to the RTL implementation and we summarize a model validation case study for a suite of pipelined Barrett multipliers.
| Original language | English |
|---|---|
| Title of host publication | NASA Formal Methods Symposium (NFM23) |
| Editors | Kristin Yvonne Rozier, Swarat Chaudhuri |
| Place of Publication | Cham |
| Publisher | Springer Nature Switzerland |
| Pages | 332-352 |
| Number of pages | 21 |
| ISBN (Print) | 978-3-031-33170-1 |
| DOIs | |
| State | Published - Jun 2023 |
| Externally published | Yes |
| Event | NASA Formal Methods Symposium (NFM23) - Duration: May 16 2023 → May 18 2023 https://conf.researchr.org/home/nfm-2023 |
Conference
| Conference | NASA Formal Methods Symposium (NFM23) |
|---|---|
| Period | 05/16/23 → 05/18/23 |
| Internet address |
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