A Timing Comparison of Different FPGA-Accelerated Load Flow Solvers

In this work, we show how an FPGA can be used to implement a load flow solver using different algorithms: Gauss-Seidel (GS) and Newton-Rhapson (NR), and we examine the timing of these algorithms. Since the bus voltages are solved iteratively, the number of iterations for one network topology to the next may be different. Due to this variability in the number of iterations, the total solving time is variable. A solver implemented in an FPGA is much faster and much more predictable in the amount of time it will take for the solving to complete, meaning that execution times for these simulations are far faster than real-time. In this work, 2 different load flow solvers, GS and NR, are compared with a detailed timing breakdown for each algorithm, given a specific network topology. We present the timing details for each part of each algorithm with an accompanying example. For the example network in this paper, the NR solver converges in fewer iterations and completes in a much shorter execution time, even though the time for each iteration is longer.